The measurement of access time in memory circuits is one of the most difficult items in integrated circuit testing. Access time is generally defined as the delay between the inputting of information to a memory circuit and the presence of valid data at the output of the memory circuit. One common parameter is the address access time, that is, the amount of delay between providing a memory cell address and the availability of the stored data at the output of the circuit. The address access times for static random access memory circuits (SRAMs) and dynamic random access memory circuits (DRAMs) are on the order of tens of nanoseconds. The brevity of the access time parameter is one factor in making the measurement difficult.
Techniques used in the past have typically relied on two or more clock signals to measure access time. This is particularly so for synchronous circuits, that is, memory devices in which the transfer of information into, within, and out of the circuit is coordinated with a clock signal. In one example of an access time measurement using multiple clocks, one clock signal is used to regulate the latching of address information and the propagation of signals within the memory circuit, while a second clock is used to regulate the outputting of data.
The multiple-clock approaches suffer from several problems. For example, die space is consumed by the pads and lines associated with additional clocks. This additional space on an integrated circuit die that is devoted only to testing the integrated circuit is often referred to as "test overhead." In addition, in a system that relies on two or more clocks, the propagation delay differences between the clock signals affect the accuracy of the access-time measurement. A need exists in the industry for a solution to these problems.